Solid state imagers using conventional CMOS technologies offer the potential of integrating many electronic functions on the same chip as the image sensor or focal plane array itself. Examples of CMOS imagers are described by A. Dickinson et al., "A 256.times.256 CMOS active-pixel image sensor with motion detection," International Solid State Circuits Conference, Digest of Technical Papers, ISSCC 1995 p 226-227; S. Mendis et al., "CMOS active pixel imager sensor," IEEE Trans. on Electron Devices, p 452, 1994 and B. Fowler et al., "A CMOS area image sensor with pixel-level A/D conversion," International Solid State Circuits Conference, Digest of Technical Papers, ISSCC 1994 p 226. The basic premise of the CMOS imager technology is that the imaging function can be performed using conventional technologies with minimal CMOS process modifications during fabrication. technologies using silicon-on-insulator (SOI) substrates have emerged as a promising technology. It is therefore desirable to construct image sensors which are compatible with CMOS on SOI.
FIG. 1 shows a graph of the absorption length in silicon versus wavelength (.mu.m). In FIG. 1, the ordinate represents light absorption length in silicon and the abscissa represents the light wavelength (.mu.m). Curve 10 in FIG. 1 shows that light in the visible range has a long absorption length, such that the photon-to-electron conversion efficiency of imaging devices using an SOI substrate would be severely reduced compared to devices using a bulk substrate due to the thickness of the silicon layer on the insulator for the absorption of radiant energy.
FIG. 2 is a graph of the quantum efficiency of photodiodes versus wavelength (.mu.m) for a SOI layer of various thickness. In FIG. 2, the ordinate represents quantum efficiency of photodiodes and the abscissa represents wavelength (.mu.m) of radiant energy. Curves 12-20 show the quantum efficiency of photodiodes for SOI epitaxial thickness of 0.01, 0.02, 0.05, 0.1, 0.2, 0.5, 1.0, 2.0 and 3.0 microns, respectively. The quantum efficiency is determined by the maximum absorption/collection depth of a SOI imaging device and would be as shown in FIG. 2. The absorption/collection depth would be the thickness of the SOI which is typically 0.2 microns or less compared to typical collection depths in bulk silicon of several microns. For imaging devices based on SOI substrates to have significant quantum efficiencies, it is necessary to provide internal gain for the photon-to-electron conversion in view of the low anticipated quantum efficiency.
Some structures have been described for obtaining bipolar gain such as a SOI MOSFET with a floating body, see for example, the publications by S. Verdonckt-Vandebroek et al., "High-gain lateral pnp bipolar action in a p-MOSFET structure," IEEE Electron Device Letters, Vol. 13, p. 312, 1992 and S. Verdonckt-Vandebroek, et al. "High-gain lateral bipolar action in a MOSFET structure," IEEE Trans. on Electron Devices, Vol. 38, p. 2487, 1991.